On 20 January 2026, China’s National Technical Committee on Integrated Circuit Standardization(SAC/TC599) opened a Call for Comment on 2026 RISC-V Standardization Project Pipeline.
- Scope of Call for Comment
- Instruction Set Standards
Translate the development of standards for the RISC-V base instruction set, extended instruction sets, privileged architecture, and instruction set peripherals.
Conduct research and formulation of China’s independent extended instruction set standards (e.g., high-performance computing extensions, matrix and tensor extensions, etc.).
- Chip Product Standards
Based on the RISC-V instruction set standard, design proprietary extended instructions tailored to specific product scenarios (e.g., IoT, data centers, model training, etc.) to achieve product differentiation.
In response to varying product performance requirements, investigate the modular design of the RISC-V instruction set and establish standardized extended instruction sets to clarify product functional boundaries, performance ceilings, and scenario adaptability.
- Develop standards for embedded RISC-V chips in consumer applications such as wearable devices, home appliances, as well as industrial control and automotive applications.
- Formulate a series of hardware and software standards for high-performance RISC-V processor chips in key domains including servers, desktops, and mobile devices.
- Establish hardware and software standards for RISC-V-based chips such as graphics processors (GPUs), tensor processors, and neural processing units (NPUs).
- Application Scenario Standards
Develop standards for application scenarios. Focus on industrial-grade scenarios such as RISC-V-based distributed control systems, industrial firewalls, and industrial computers; IoT scenarios including smart homes and smart health eldercare; automotive electronics scenarios; new urban infrastructure scenarios; aerospace scenarios such as drones and BeiDou navigation; and emerging application scenarios like intelligent computing centers and next-generation storage.
Carry out the development of standards for digital infrastructure construction, engineering specifications, and application guidelines based on the RISC-V architecture.
- Ecosystem Development Standards
Develop standards covering critical processes in chip design, including intellectual property (IP) core development, full-stack IP platforms, high-quality standardized micro-kernels, and process design kits.
Leverage the open-source and open nature of RISC-V to formulate standards for software compilers and toolchains, firmware, system enabling, and other related components.
Establish standards for testing and evaluation, certification and assessment, testing tools, and other testing and evaluation frameworks.
- Service Assurance Standards
Standards for talent cultivation, intellectual property, enterprise services, digital infrastructure, and related service areas.
- Submission Materials
The applying unit shall submit a proposal for national or industry standard project initiation along with a draft standard (providing the draft structure and main technical parameter framework; specific indicators may be omitted).
For details, please refer to the attachment below. Please note that all these forms are presented in Chinese. If you need any assistance with the Call for Comment, please contact us via email at any time: assistant@sesec.eu
Annex1.National Standards Recommendation Form
Annex2.National Standards Draft Template
Annex3. Sector Standards Recommendation Form
Annex4. Sector Standards Draft Template
- Submission Timeline and Method
Deadline: 13th February 2026, email to niwanj@cesi.cn (NI Wanjing) or wangyg@cesi.cn (WANG Yigang)
SESEC Observation
RISC-V, as an open instruction set architecture, is driving global innovation in computing. To advance China’s RISC-V ecosystem, the RISC-V Working Group under the National Technical Committee of Integrated Circuit Standardization is leading the development of a comprehensive standards system spanning the entire industry chain – from instruction set architecture and chip design to testing, application scenarios, and service support.
Through the formulation of national and industry standards, the initiative aims to accelerate the translation of technological achievements into practical applications, fostering deep integration and synergistic growth between industrial development and technological innovation.
SESEC recommends EU stakeholders to strategically participate in this Call for Comment to gain visibility and influence China’s RISC-V standardization, while safeguarding European IP and aligning engagement with coordinated EU initiatives to promote global interoperability.
If you need any assistance with the Call for Comment, please contact us via email at any time: assistant@sesec.eu
Original Announcement from: https://mp.weixin.qq.com/s/RtkbkPbI26Sjg1PIcViW9w?scene=1
